Programmable gate arrays, sometimes containing over one million transistors, are frequently used to create economical Application Specific Integrated Circuits (ASIC). A programmable gate array may be metal mask programmable, electrically programmable, or laser programmable. In a mask programmable gate array, the silicon die containing the unconnected transistors is called a master slice or master image. A user who wishes to customize a master slice uses well-known software programs and predefined logic circuit configurations (macrocells) contained in a macrocell library to selectively interconnect the transistors within the gate array to provide an ASIC.
In one type of metal mask programmable gate array, an array of cells is formed on a chip wherein each cell is comprised of a plurality of unconnected components. In a typical arrangement, there is a variety of types of components in each cell to enable a designer of the macrocells to create various kinds of logic circuits within each cell or by using a combination of cells. Ideally, each cell should contain an optimum number and variety of components so that the designer may create a wide variety of macrocells using the shortest interconnect wire lengths, using a minimum amount of die area, and using other techniques for achieving high performance for-each macrocell.
In a programmable gate array structure, CMOS transistors frequently comprise the components of a cell due to the low power consumption of a CMOS device, where an N-channel and a P-channel MOSFET are connected in series between a power supply terminal and ground. Because the gates of these CMOS transistors are made common, one transistor will be off while the other transistor will be on, thus avoiding a low impedance path between the power supply terminal and ground. These CMOS transistors may be used as building blocks to create a wide variety of macrocells.
Since die area is limited, it is desirable to make the CMOS transistors small, resulting in the CMOS transistors typically having only moderate current handling capability. To overcome any excessive parasitic capacitance, inductance, and resistance of conductors and components connecting the output of the CMOS transistors to one or more subsequent stages, either a plurality of CMOS transistors must be connected in parallel to source or sink a large output current or, alternatively, high current drivers may be incorporated in the integrated circuit. Drivers may be located within each cell to amplify the low current output of the CMOS transistors within the cell or may be located only in selected areas of the chip.
One type of semiconductor technology which has become increasingly popular due to its fast switching speed and high output drive current is referred to as BiCMOS technology. In a BiCMOS circuit, bipolar transistors may be used as the drivers, since their switching speed can be significantly faster than MOSFETs of the same size.
In one prior art cell of a BiCMOS gate array, a plurality of CMOS transistors are contained within each cell along with two bipolar devices for use as the driver. A prior art cell containing these two bipolar transistors is described in the article entitled, "A High Density BiCMOS Direct Drive Array," by Wong et al., IEEE, 1988 CICC. This article describes an improvement over previous BiCMOS gate arrays which generally include the bipolar driver stage in each of the cells. Since, according to the article, a driver is not needed for every macrocell, cells containing the bipolar driver transistors are only located around the periphery of an internal core of CMOS logic gates. In this prior art device, each BiCMOS block consists of two CMOS logic gates, four additional N-channel MOSFETs, and two NPN bipolar transistors. The BiCMOS blocks described in this prior art article are used to build high speed and high drive circuits. However, if an internal pure CMOS cell requires a peripheral bipolar transistor driver, long interconnect lines are needed, which incur delay.
Thus, as evidenced by the above-mentioned article and its improvement over the prior art, prior art BiCMOS programmable gate array designs have included either a majority of BiCMOS cells (each having two bipolar transistors) or only a limited number of BiCMOS cells arranged along the periphery of the chip.
CMOS components contained in these prior art BiCMOS and standard CMOS cells are made fairly large to drive typical loads of, for example, 0.4 pF without the use of the bipolar driver. Also, a conventional BiCMOS circuit, when using two bipolar transistors for a driver, requires a number of MOSFETs to buffer the base of the pull-down NPN bipolar transistor to prevent a high voltage (e.g., 5 volts) input signal from being directly applied to the base of the NPN pull-down transistor to avoid drawing a high base current. Thus, in these prior art BiCMOS cells and standard CMOS cells, due to a cells' requirement to adequately drive one or more subsequent stages, the compute capability of a cell per die area is relatively low. Hence, BiCMOS and CMOS programmable gate arrays make relatively inefficient use of die area.
Additionally, since the bipolar transistor driver is not ultimately connected in most macrocells actually used in an ASIC because their drive power is not required to drive one or more subsequent stages, the relatively large amount of die area dedicated to the bipolar transistor drivers is wasted. Further, it is not desireable to use drivers when driving a low to moderate capacitance load, since the CMOS transistors can, by themselves, adequately drive these loads, and the drivers would thus incur an unnecessary switching delay.
It is also common practice to include BiCMOS cells as input/output (I/O) drivers, where each BiCMOS I/O cell is associated with a pin of the chip; however these BiCMOS cells are not typically used for internal driving requirements.
Accordingly, what is needed in the field of programmable gate arrays is a cell which achieves the same or higher performance as existing BiCMOS gate arrays as well as achieves a higher compute capability per die area than CMOS and BiCMOS gate arrays.